vhd file
Код: Выбрать все
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LED_Blinker is
Port ( LED : buffer STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
SEC : out INTEGER);
end LED_Blinker;
architecture Behavioral of LED_Blinker is
signal counter : INTEGER := 0;
constant clock_frequency : INTEGER := 50000000; -- Частота тактового сигнала, например, 50 МГц
constant blink_rate : INTEGER := clock_frequency; -- 1 Гц
constant count_rate : INTEGER := clock_frequency; -- Счет каждую секунду
signal blink : BOOLEAN := TRUE;
begin
process(CLK, RST)
begin
if RST = '1' then
counter <= 0;
elsif rising_edge(CLK) then
if counter = count_rate - 1 then
blink<=not blink;
counter <= 0;
if blink then
LED<= '1';
else
LED<= '0';
end if;
else
counter <= counter + 1;
end if;
end if;
end process;
SEC <= counter;
end Behavioral;
ucf pins file
Код: Выбрать все
NET "clk" LOC = T8 | TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 50000 kHz;
##
##
NET "LED" LOC = P4;
# PlanAhead Generated IO constraints
NET "LED" IOSTANDARD = LVCMOS33;